library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity bcd2sevenseg is
port (
      digit_selection_in    : in std_logic;                     -- Digit Selection input
      bcd                   : in std_logic_vector(3 downto 0);  -- BCD input
      seven_segment         : out std_logic_vector(6 downto 0); -- 7-segment output MSBit is g, LSBit is a
      digit_selection_out   : out std_logic                     -- Digit Selection Pin for PmodSSD
    );
end bcd2sevenseg;

architecture Behavioral of bcd2sevenseg is

begin
-- Insert your code here
-- Use ONLY process with case statement

end Behavioral;